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some questions regard the H3 boards

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Published in 2015-3-23 00:05:55 | Show all floors |Read mode
On the boards is there a PMIC (AXPxxx) for the H3 processor?
What is the exact clockrate of the H3? realy 1.6GHz?
what is the "internal" name of the H3? sun8i?

thanks for responding
Boards:
orangepi plus, olinuxino A20, cubieboard A10, mele A2000 .....
Published in 2015-11-27 08:39:04 | Show all floors
And this is how it looks if you're not following the overvoltage route but go instead in the other direction. I did some undervolting, used cpuburn-a7 and cpufreq-ljt-stress-test to ensure stability and data integrity and gave sysbench again a try:

Exactly the same performance @ 1.2 GHz (still 158.2 seconds) but 10°C less under full load caused by 80mV less voltage:

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 Author| Published in 2015-3-25 13:06:08 | Show all floors
"internal" name is sun8iw7p1

Boards:
orangepi plus, olinuxino A20, cubieboard A10, mele A2000 .....
Published in 2015-3-25 14:42:15 | Show all floors
up to 1536MHZ.
Published in 2015-3-25 14:43:46 | Show all floors
If Heat dissipation is good, can up to 1.6GHZ.

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 Author| Published in 2015-3-25 15:04:26 | Show all floors
OK thanks
PMIC seems not needed, at least i dont see it on the pictures.
Boards:
orangepi plus, olinuxino A20, cubieboard A10, mele A2000 .....

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 Author| Published in 2015-3-25 17:41:45 | Show all floors
For the clock-rate :

; extremity_freq(Hz): cpu extremity frequency when run benckmark or demo apk
;                     1536MHz@1500mV with radiator, 1296MHz@1340mV without radiator
; max_freq: cpu maximum frequency, based on Hz, can not be more than 1200MHz
; min_freq: cpu minimum frequency, based on Hz, can not be less than 60MHz

Well at least 1296MHz@1340mV without radiator
Boards:
orangepi plus, olinuxino A20, cubieboard A10, mele A2000 .....
Published in 2015-3-25 18:57:25 | Show all floors
You are right.

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Published in 2015-5-18 08:56:39 | Show all floors
I have another question. According to datasheet Allwinner H3 has 3(!) USB 2.0 HS Hosts (480Mbps, each!) and one USB OTG.
But, as I seen on Orange Pi photo, engineers decided to use USB-hub chip.
Why they decided so? In my opinion It would be better to use 3 USB-buses, than only one.
Published in 2015-11-23 15:35:15 | Show all floors
Edited by bronco at 2015-11-23 15:40
dvl36 replied at 2015-5-18 08:56
Allwinner H3 has 3(!) USB 2.0 HS Hosts (480Mbps, each!) and one USB OTG. ... In my opinion It would be better to use 3 USB-buses, than only one.

I believe they did so since when starting with the "Banana Pi Plus" they realized that the H3 has no SATA any longer which would be a step backwards compared to the 2 Banana Pi clones they sold before (Orange Pi and Mini -- both with A20 and native SATA).

So they put an old/crappy GL830 USB-to-SATA bridge (slow, no UASP, 2TB limitation) on the PCB and sold the 'Pi Plus' as being SATA capable (which it is not). Therefore only 2 USB host ports left. But since the model was called 'Plus' they decided to make things even worse and use an internal USB hub also so that all 4 USB ports have to share the bandwidth of one single USB2.0 connection (almost as worse as with the RPi where everything has to share a single USB2.0 connection). But Xunlong was right since customers didn't care and didn't realize that more is less when it's about more externally available USB ports compared to the SoC's.

Fortunately the internal USB hub is gone on the OPi PC and there all 4 USB ports can be used without sharing bandwidth. That would increase potential I/O bandwidth by factor 2 compared to the more expensive H3 based Orange Pis




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Published in 2015-11-23 23:06:06 | Show all floors
fritz replied at 2015-3-25 17:41
For the clock-rate :

; extremity_freq(Hz): cpu extremity frequency when run benckmark or demo apk

I think it would make more sense to have default configuration for up to 1200Mhz, since everything more is basicly overclocking the thing.

So in reality, it's false advertising on the OrangePi part, since the SoC is only rated for 1200Mhz, everything else is overclock (which could potentially be unstable).
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