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Orange PI R1 / Allwinner Ethernet PHY

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Post time 2018-6-6 19:53:02 | Show all posts |Read mode
I'm currently using an Orange board PI R1, that have 2 ethernet, one came from internal H2+ EMAC and EPHY, the other is an USB bridge

I have a full custom setup (based on armbian Linux version 4.13.9+ (root@bat-virtual-machine) (gcc version 7.1.1 20170707 (Linaro GCC 7.1-2017.08)) #113 SMP PREEMPT). I only used kernel, then have custom init and app.


I use ethernet in USB bridge like standard one (Linux kernel driver, TCPs sockets on it), I can reach 5Mo/s in both way (at same time), and that enough for my app.
Internal EMAC/EPHY is handled directly by my kernel module, has I'm using Ethercat protocol. Specific point, is that it use full duplex, frame go out and will came back during emission (let's say 10 µs delay)

I solved all software issue, it's stable.

But I see some random packet corruption. I've tracked it down to PHY saying that it see incorrect symbol (avaible in packet descriptor), CRC is not good. Using known data, I clearly see that there is 1 or 2 bytes afftected on frame. For ex 0x00 => 0x40, or 0x00 => 0x0C.

PER is quite slow but depend on product on other side.

I have 1800 packet/s

With an Ethercat product, I have an error each 5mn (540k packet)
With an ethercat hub (it have a more stable, shorter delay),  I have an error each 2 hours (12M packet)
Error are not in specific packet position.


If a do a direct TX=>RX loopback at RJ45 connector, I have no error in 24h (that's my target). Note : with other hardware, I reach this target with same Ethercat product and hub.


I've tried various thing on hardware, trying to filter power, filter PHY power (1.1V), have a better power (it's 1.2V lowered by a serial resistor), filter general power. Tried also another RJ45 filtered jack. Tried on a second board. Tried to filter ethernet signal in case of spike and so on.

I mis the exact schematic of Orange PI R1 board (one in web site is not the good one), and exact board layout.


I tried also to read internal PHY registers. But I have not the documentation of internal MDIO registers.
The best I have is, I also found another driver in paste.bin :
https://github.com/allwinner-zh/ ... et/phy/sunxi-ephy.c


Specifically theses registers in extended pages:
The PHY is a Sunplus core IP (guess by OUI identifier). But I didn't find any documentation (even on another product of Sunplus or Allwinner) that can describe theses PHY registers.
Idea is to tweak some delay if possible ...


[tr]        [/tr]
        phy_write(phydev, 0x1f, 0x0200);        /* Switch to Page 2 */
[tr]        [/tr]
        phy_write(phydev, 0x18, 0x0000);        /* PHYAFE TRX optimization */
[tr]        [/tr]

[tr]        [/tr]
        phy_write(phydev, 0x1f, 0x0600);        /* Switch to Page 6 */
[tr]        [/tr]
        phy_write(phydev, 0x14, 0x708f);        /* PHYAFE TX optimization */
[tr]        [/tr]
        phy_write(phydev, 0x13, 0xF000);        /* PHYAFE RX optimization */
[tr]        [/tr]
        phy_write(phydev, 0x15, 0x1530);
[tr]        [/tr]

[tr]        [/tr]
        phy_write(phydev, 0x1f, 0x0800);        /* Switch to Page 6 */
        phy_write(phydev, 0x18, 0x00bc);        /* PHYAFE TRX optimization */[tr]        [/tr]



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